I read the whitepaper of glitch on arxiv and the presentation of glitching the tegra, but didn't find that the signal of the gate might give an issue.Or maybe we need to also pay attention to these switching characteristic value?
Also it can be that different brand states or we call it promote their specs differently.
Will update tomorrow.
Comparing the datasheet also difficult, IRF using [email protected] while AON using 10V
Lets say we add the total time (turn on delay + rise time + turn off delay + fall time)
[email protected]
IRF8342: 31.1ns
IRF8714: 35.9ns
NP2016: 86ns
VGS@10V
AON7400: 40.1ns
AON6512: 56.1ns
If we sees from the pattern it seems not. We might think that higher ns will result longer/unstable glitch, but NP2016 is the one people say hwfly use, and i assume its <15sec to glitch, eventhough they have the highest time spec.
Post automatically merged:
The base of why i think Rds is important because the apu have impedance. And in here we make a parallel circuit. So the resistance of the mosfet, will also affect how much the current flows to that point (i assume its somekind of the VDD of the processor). First i think that the lesser the current flows to the apu the better, that why i think 6512 is the best of all, since it is the most less resistance, so majority of the current will be goes to the mosfet. But from your finding, i might be wrong. The current flows in the apu must be at some range, for the glitch to work flawlessly.Or maybe we need to also pay attention to these switching characteristic value?
Also it can be that different brand states or we call it promote their specs differently.
Will update tomorrow.
Last edited by abal1000x,